Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling copper in features or cavities etched into the dielectric interlayers by a metallization process. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential interlayers can be electrically connected using vias or contacts.
In a typical process, first an insulating interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. Typically the width of the trenches is larger than the width of the vias. Then, copper is electroplated to fill the features. Once the plating is over, a chemical mechanical polishing (CMP) step is conducted to remove the excess copper layer and other conductive layers that are above the top surface of the substrate to form the interconnect structure. These processes are repeated multiple times to manufacture multi layer interconnects.
An exemplary prior art process can be briefly described with the help of FIGS. 1A and 1B. FIG. 1A shows a substrate 8 which is processed to form an exemplary dual damascene structure shown in FIG. 1B. In this structure, a via 10 and a trench 12 are formed in an isolating layer 14 on the substrate 8, and filled with copper 16 through electroplating process. Conventionally, after patterning and etching which form the cavities such as vias and trenches, the isolating layer 14 is first coated with a barrier layer 18, for example, a Ta/TaN composite layer. The barrier layer 18 coats the insulating layer to ensure good adhesion and acts as a barrier material to prevent diffusion of the copper into the insulating layers and into the semiconductor devices. Next, a seed layer (not shown), which is often a copper layer, is deposited on the barrier layer. The seed layer forms a conductive material base for copper crystal growth during the subsequent copper deposition. As the copper film is electroplated, the copper 16 quickly fills the small via 10 but coats the wide trench and the surface in a conformal manner. When the deposition process is continued, the trench is also filled with copper, but with a step ‘s’ and a thick copper layer ‘t’. Thick copper on the surface presents a problem during CMP step that is expensive and time consuming. As shown in FIG. 1B, during the CMP removal of the thick copper layer on the trench 12 and the barrier layer 18 on the top surface, a non-planar 20 surface may be formed on the remaining surface of the copper layer. The non-planar surface may form due to the difference in polishing rate between the barrier layer and the copper. The non-planar surface 20, or so called “dishing effect”, adversely affects the quality of the subsequently deposited layers.
Some prior art processes attempt to minimize or eliminate the dishing effect by employing multiple polishing steps with different slurries and polishing pads. For example, in one particular prior art process, at a first CMP process step the bulk copper layer on the substrate is removed down to a thickness that is over the barrier layer. The first step is performed in a first CMP station with a polishing pad that has no abrasive particles. A second step is performed in a second CMP station that has a pad with fixed abrasives to expose a portion of the barrier layer that overlies the insulating layer. In a third step, the portion of the barrier layer that overlies the insulating layer is removed using a pad that has no fixed particles. The third step is performed in a third CMP station.
In such prior art processes, multiple polishing steps increase the production time and the production cost. To this end, there is a need for an alternative method of planarizing plated substrates.